A voltage control type variable resistor using MIS (which is referred to as MIS variable resistor herein) by conventional art is shown in FIG. 1. There has been proposed such a structure, for instance, that semiconductor regions 3 and 4 of N.sup.+ type are formed from the surface 2 into a semiconductor substrate 1 of p type, an electrode 7 is placed on an insulated layer 6 from the side of the surface 2 on a region 5 between the regions 3 and 4 of the semiconductor, and the region 3 is connected with the substrate 1 to be lead out at a terminal 8 while the region 4 and the electrode 7 are lead out at terminals 9 and 10 respectrively.
In an MIS variable resistor having such a construction using the semiconductor substrate 1, the semiconductor region 3 is used as a source S, the region 4 as a drain D, the region 5 as a channel region, the insulated layer 6 as a gate insulated film and the electrode 7 as a gate G
By constructing in the manner above, there is formed what is called the self-aligned gate MIS transistor Q. If the terminals 8 and 10 are used as the control terminals, a variable voltage source 11 is connected therebetween, i.e. between the source S and the gate G, and if the voltage of the variable voltage source 11 is varied, a resistance corresponding to the voltage of the variable voltage source 11 exists between the resistance terminal 8 and 9 or, between the source S and the drain D. The MIS variable resistor functions as a variable resistor of the voltage control type in the above mentioned manner.
In the case of prior art MIS variable resistors, however, when a reverse voltage with the positive side on the source S is applied between the terminals 8 and 9 or between the source S and the drain D, because the PN junction 12 between the drain D and the semiconductor substrate 1 is biased to the forward direction, an electric current flows through the PN junction 12. The value on the negative side of the voltage V.sub.D of the drain D based upon the source S is therefore limited to be an extremely small value, for instance, about -0.7 V in order to prevent such current. In FIG. 2, the drain voltage is plotted on the abscissa while the drain current is plotted on the ordinate. The solid line shows the resistance value in the case where a control voltage is applied to the control terminals 10 and 8 as to make the resistance small between the resistance terminals 8 and 9 while the dot-and-chain shows the resistance value in the case where the control voltage is applied thereto so as to make the resistance larger.
As is obvious from FIG. 2, the prior art device is defective in that it is not applicable over a wider range of drain voltages V.sub.D.
As the MIS transistor Q is of the self-aligned type in the conventional MIS variable resistor shown in FIG. 1, the linear region characteristics of the drain current I.sub.D against the drain voltage V.sub.D ' especially when a larger resistance value is obtained, is extremely limited, and therefore the applicable region of the resistor or the dynamic range thereof is inconveniently narrow.